Frequency synthesisers have been developed in recent years which permit direct modulation of a carrier signal generated by a Phase Locked Loop (PLL) circuit by rapidly varying the instantaneous value of a variable divider forming part of the PLL circuit; the variable divider is controlled by a digital signal output from a sigma-delta type multi-accumulator digital circuit which acts to shape the noise generated by such a system so that it mostly occurs at higher frequencies where it can be more easily filtered out (by the natural Low Pass Filter behavior of the closed PLL) before transmission of the signal. Such frequency synthesisers are known as direct modulation multi-accumulator fractional-N synthesisers and an example of such a synthesiser is described in U.S. Pat. No. 5,166,642 which is incorporated herein by way of reference.
Such frequency synthesisers are able to produce very well controlled modulation with a low enough Signal to Noise Ratio (SNR)--and in particular Signal to Phase-Noise Ratio--at relatively low modulation frequencies to find many practical applications. However, as a result of the type of noise shaping employed by the multi-accumulator digital circuit, it is difficult to maintain such a low SNR where a higher bandwidth is required for the modulation signal. This is because the noise shaping reduces the amount of low frequency noise at the expense of increasing the amount of high frequency noise. For this reason, multi-accumulator fractional-N frequency synthesisers have not found application in large modulation bandwidth applications to date.